1. Field of the Invention
The present invention relates in general to the field of signal processing, and, more specifically, to a power factor correction controller with a power supply DC offset detector.
2. Description of the Related Art
Power control systems provide power factor corrected and regulated output voltages to many devices that utilize a regulated output voltage. FIG. 1 depicts a power control system 100, which includes a switching power converter 102. The switching power converter 102 performs power factor correction and provides constant voltage power to load 112. Voltage source 101 supplies an alternating current (AC) input voltage Vin(t) to a full, diode bridge rectifier 103. The voltage source 101 is, for example, a public utility, and the AC voltage Vin(t) is, for example, a 60 Hz/110 V line voltage in the United States of America or a 50 Hz/220 V line voltage in Europe. The rectifier 103 rectifies the input voltage Vin(t) and supplies a rectified, time-varying, line input voltage Vx(t) to the switching power converter.
The switching power converter 102 includes power factor correction (PFC) stage 124 and driver stage 126. The PFC stage 124 is controlled by switch 108 and provides power factor correction. The driver stage 126 is also controlled by switch 108 and regulates the transfer of energy from the line input voltage Vx(t) through inductor 110 to capacitor 106. The inductor current iL ramps ‘up’ when the switch 108 conducts, i.e. is “ON”. The inductor current iL ramps down when switch 108 is nonconductive, i.e. is “OFF”, and supplies current iL to recharge capacitor 106. The time period during which inductor current iL ramps down is commonly referred to as the “inductor flyback time”. In at least one embodiment, the switching power converter 102 operates in discontinuous current mode, i.e. the inductor current iL ramp up time plus the inductor flyback time is less than the period of switch 108.
Capacitor 106 supplies stored energy to load 112 while the switch 108 conducts. The capacitor 106 is sufficiently large so as to maintain a substantially constant output voltage Vc(t), as established by a power factor correction (PFC) and output voltage controller 114 (as discussed in more detail below). The output voltage Vc(t) remains substantially constant during constant load conditions. However, as load conditions change, the output voltage Vc(t) changes. The PFC and output voltage controller 114 responds to the changes in Vc(t) and adjusts the control signal CS0 to maintain a substantially constant output voltage as quickly as possible. The output voltage controller 114 includes a small capacitor 115 to filter any high frequency signals from the line input voltage Vx(t).
The power control system 100 also includes a PFC and output voltage controller 114 to control the switch 108 and, thus, control power factor correction and regulate output power of the switching power converter 102. The goal of power factor correction technology is to make the switching power converter 102 appear resistive to the voltage source 101. Thus, the PFC and output voltage controller 114 attempts to control the inductor current iL so that the average inductor current iL is linearly and directly related to the line input voltage Vx(t). Prodić, Compensator Design and Stability Assessment for Fast Voltage Loops of Power Factor Correction Rectifiers, IEEE Transactions on Power Electronics, Vol. 22, No. 5, September 2007, pp. 1719-1729 (referred to herein as “Prodić”), describes an example of PFC and output voltage controller 114. The PFC and output voltage controller 114 supplies a pulse width modified (PWM) control signal CS0 to control the conductivity of switch 108. In at least one embodiment, switch 108 is a field effect transistor (FET), and control signal CS0 is the gate voltage of switch 108. The values of the pulse width and duty cycle of control signal CS0 depend on two feedback signals, namely, the line input voltage Vx(t) and the capacitor voltage/output voltage Vc(t).
Switching power converter 114 receives two feedback signals, the line input voltage Vx(t) and the output voltage Vc(t), via a wide bandwidth current loop 116 and a slower voltage loop 118. The line input voltage Vx(t) is sensed from node 120 between the diode rectifier and inductor 110. The output voltage Vc(t) is sensed from node 122 between diode 111 and load 112. The current loop 116 operates at a frequency fc that is sufficient to allow the PFC and output controller 114 to respond to changes in the line input voltage Vx(t) and cause the inductor current iL to track the line input voltage to provide power factor correction. The current loop frequency is generally set to a value between 20 kHz and 150 kHz. The voltage loop 118 operates at a much slower frequency fv, typically 10-20 Hz. As subsequently described in more detail, the capacitor voltage Vc(t) includes an AC component (sometimes referred to herein as a “ripple”) having a frequency equal to twice the frequency of input voltage Vin(t), e.g. 120 Hz. Thus, by operating at 10-20 Hz, the voltage loop 118 functions as a low pass filter to filter the ripple component.
FIG. 2 depicts an output voltage Vc(t) versus time graph 200. Referring to FIGS. 1 and 2, the output voltage Vc(t) supplied by power control system 100 includes a direct current (DC) component, i.e. the DC offset for voltage Vc(t), and an exemplary AC component, e.g. ripple 202. Ripple 202 is generally triangular shaped. However, ripple 202 can be any waveform. Ripple 202 is depicted with a “dense” line because ripple 202 generally contains many high frequency noise perturbations. The noise is, for example, caused by noise across the inductor 110 and noise from load 112. In at least one embodiment, load 112 includes another switching power converter, and an inductor corresponding to inductor 110 can cause noise to appear at the output of switching power converter 102. Thus, ripple 202 is generally not a ‘clean’ waveform, such as a sine wave. Rather, ripple 202 has, for example, a generally triangular shape with many noise perturbations. The primary frequency fR of the ripple 202 is twice the line frequency fL of input voltage Vin(t). For example, for a line frequency fL=60 Hz, the ripple frequency fR=2·fL=2·60 Hz=120 Hz. The DC offset for voltage Vc(t) can change over time due to input power fluctuations and load power demand fluctuations. Thus, the PFC and output voltage controller 114 monitors the output voltage Vc(t) and adjusts the control signal CS0 to return the output voltage Vc(t) to the desired value.
The ripple 202 can adversely influence the determination of the control signal CS0 by PFC and output voltage controller 114. To minimize the influence of ripple 202 on the control signal CS0, the voltage loop 118 operates at a much slower frequency fv, typically 10-20 Hz, than the line frequency fL. By operating at 10-20 Hz, the voltage loop 118 functions as a low pass filter to filter out ripple 202. However, operating at 10-20 Hz also slows the response of PFC and output voltage controller 114 to changes in the output voltage Vc(t).
FIG. 3 depicts a generalized representation of a power control system 300 described in Prodić. The PFC and output voltage controller 302 of Prodić includes an error generator 304 to determine an error signal ed(t). The error signal ed(t) represents a difference between the output voltage Vc(t) and a reference voltage VREF. The reference voltage VREF is set to the desired value of output voltage Vc(t). A comb filter 306 filters the error signal ed(t). The comb filter 306 has significant attenuation at equally spaced frequencies (referred to as “notches”) and has unity gain at other frequencies. The comb filter 306 automatically tunes the notches to match twice the line frequency fL and harmonics of the line frequency. According to Prodić, the comb filter 306 generates a “ripple free” error signal evf(t). Compensator 308 processes the filtered error signal and input voltage feedback signal Vx(t) generates a compensator output signal. The pulse width modulator (PWM) 310 processes the compensator output signal to generate control signal CS0. However, the comb filter 306 notches should be accurate to precisely match the line frequency fL and harmonics thereof and avoid aliasing.